1. Field of the Invention
The present invention relates to a semiconductor device primarily intended for mixed-signal and analog applications which incorporates devices to perform logic operations and devices to perform an Input/Output (I/O) function, and a manufacturing method thereof, and more particularly to a semiconductor device including Castellated-Gate MOSFET devices capable of Fully-Depleted operation and complimentary MOS (CMOS) transistors functioning as logic devices, and to a manufacturing method thereof.
2. Related Applications
An application related to the present invention is entitled “An Improved Fully-Depleted Castellated Gate MOSFET Device and Method of Manufacture Thereof”, Ser. No. 10/940,093 filed Sep. 13, 2004. The related application listed above has been assigned to the Assignee of the present invention.
3. Description of the Prior Art
In complex systems that perform signal processing, power management, and computing operations, the logical, analog, and other functions are often performed by various and often different semiconductor device structures that are fabricated by various manufacturing methods. In the effort to reduce system cost, increase performance, or increase reliability, one or more of these manufacturing methods are often integrated to create a semiconductor device that can perform a greater variety of functions on a single chip. In the field of analog, mixed-signal, and power electronics in particular, technologies that combine different types of active devices onto a common wafer substrate are quite prevalent. Some examples of these semiconductor technology platforms include U.S. Pat. Nos. 3,404,450, 4,475,279, 4,960,726, 6,288,427, and 6,392,275.
More particularly, in the area of analog and mixed-signal semiconductor VLSI devices involved in high-speed communications, the Input/Output (I/O) device must be able to drive relatively large loads, while simultaneously being robust from a reliability standpoint, as it may be used or exist in a less-controlled signaling environment than found in all-digital systems The aforementioned device performance characteristics are often at odds with those of the devices that perform low power logic and/or computing functions within modem, highly integrated VLSI chips, including Application-Specific-Integrated-Circuits (ASICs), Application-Specific-Standard-Products (ASSPs), Field Programmable Gate Arrays (FPGAs), or Systems-On-A-Chip (SoCs). In silicon-based technologies at the present time, these logic and computing functions are overwhelmingly performed by Complimentary Metal Oxide Semiconductor devices (CMOS).
The progression of CMOS device scaling, that is planer MOSFET, has seen a continuous shrinking of transistor dimensions in both the vertical and the horizontal dimensions resulting in an approximate doubling of the number of transistors per unit area every 18 months or so. From the economics perspective, this scaling progression has resulted in CMOS becoming the preeminent technology for packing system functions on a microchip. The desire to shrink MOSFET gate channel lengths and hence area, as width-to-length ratios remain roughly constant, requires the simultaneous vertical scaling of both the gate oxide and the source/drain junctions. This creates the requirement that the power supply (Vdd) also scale, as indicated above. The power supply voltage must scale so as to maintain gate oxide integrity (breakdown/wear-out due to voltage stress), to provide adequate junction breakdown margin, and to minimize device lifetime reduction due to hot carrier injection. Unfortunately, while CMOS scaling has enabled the circuit and system designer to pack a tremendous amount of functionality onto a silicon die, it has simultaneously created a number of significant problems as far as the chip's ability to interface with the outside world.
The CMOS device scaling behavior, discussed above, combined with the continuing drive to utilize semiconductor chip area while maintaining I/O compatibility has resulted in the evolution of baseline CMOS ASIC/SOC process technologies that now have two or more gate oxides to account for the need to operate efficiently at two, and sometimes three, power supply levels. Having begun at roughly the 0.25 um node, this is currently the approach taken by certain mainstream ASIC/ASSP semiconductor producers or foundries. These technology offerings generally consist of a baseline process flow that has a fully scaled and optimized thin oxide core device to the extent that the current process manufacturing technology allows, and a thick oxide device which is essentially the core device from the previous technology generation. Unfortunately, in such technology evolution, the thick oxide I/O device has become somewhat of a “forgotten stepchild”, as only the thin-oxide core devices can truly take advantage of the shrinking feature sizes that are enabled by state-of-the-art photolithography. More importantly, as the thick oxide device is a “leftover” from the previous technology node, it typically under-performs the thin-oxide core device in terms of speed/bandwidth (ft).
In addition to the speed performance and oxide reliability issues stated above, a number of other I/O robustness issues arise in analog and mixed-signal applications. These issues include EMI (electromagnetic interference)/ESD (electrostatic discharge), and more generally, EOS (electromagnetic overstress). For example a power amplifier must be able to withstand a high VSWR (voltage standing wave ratio) in the event that its output load becomes mismatched during transmission. In a second example, Latch-Up phenomenon must also be taken into account when using bulk-wafer based semiconductor devices, which can pose additional challenges in analog and mixed-signal applications. Consequently, while CMOS technology scaling provides a clear path to a greater degree of chip-level system integration in the digital domain, the scaling behavior of the planer CMOS transistor does not provide equivalent advantages in the area of analog and mixed-signal I/O.
At present, BiCMOS (bipolar-CMOS combination) technologies, and particularly SiGe bipolar, offer a solution to some of the problems discussed above. However, a number of difficulties persist including, in particular, power consumption, cost and scalability. Bipolar devices consume significantly more power than CMOS devices, which increases package cost and at some point renders them unsuitable as a system solution, in particular for portable devices. From the standpoint of scaling, bipolar technologies have hit an apparent limit in terms of increasing performance for a given density and power consumption. Bipolar devices by nature, like the thick oxide CMOS I/O devices discussed earlier, cannot take full advantage of decreasing feature sizes which result from advances in wafer patterning technology (photolithography). The integration of CMOS and bipolar devices (BiCMOS) reduces the power consumption problem but leads to a second difficulty, i.e. cost. High performance technologies, such as SiGe BiCMOS cost upwards of 25% or more than CMOS-only devices at the same feature sizes. Finally, the combined SiGe BiCMOS technology platform faces another very significant cost related obstacle: manufacturability. The production of SiGe NPN bipolar devices involves the formation of a very delicate Germanium doping profile which requires stringent process control. The sensitivity of the resulting NPN device to thermal processing generally means that it must be added last in the BiCMOS process sequence. Consequently the core digital devices must absorb the effects of additional thermal and plasma processes, many of which can lead to device parametric shifts and subsequent parametric yield loss. While sophisticated SiGe BiCMOS technologies have been demonstrated at MOSFET gate lengths down to 90 nm on 300 mm wafers, future nanoscale CMOS, or other digital core technologies are likely to require physical structures (strained Si/SiGe, high-k gates) that may be as delicate and sensitive from a process integration perspective, as the SiGe bipolar base structure; this trade-off could be a major obstacle in a combined mixed-signal SoC platform.
Clearly, the trends and problems discussed above may soon create a situation where it is no longer desirable to integrate a significant amount of analog functionality into a single-chip mixed-signal system solution, thus eliminating one of the traditional paths to reduce cost and power consumption in electronic systems. Accordingly, there is a need for a new type of combined silicon technology platform that takes advantage of the low power and economic advantages of CMOS in addition to enhancing the I/O function through decreasing feature sizes. There continues to be development of technology platforms which overcome some of the aforementioned problems. Some specific recent examples of these efforts are illustrated in U.S. Pat. Nos. 6,756,274 and 6,806,554. In other more-specific developments related to the present invention, the combination of planer MOSFETs and vertical FinFETs (e.g. a single channel castellated-gate MOSFET) have recently been published by Masahara et.al., “A Novel Process for Co-Integration of Vertical Double-Gate and Planar Single-Gate MOSFETs” IEEE DRC #61 (2003), pp. 49-50. In this case however, the combination of these two device types was proposed for core logic applications to solve the problem of a lack of channel length design selectability in the case where the vertical dimension of the fin defines the device channel length; this is a substantially different problem than the one solved by the invention disclosed herein. In spite of these recent developments in the art, a number of problems continue to persist. Therefore, there remains a need in the art for a silicon semiconductor device and technology platform that combines a high density core device technology for logic and computing functions with a high performance I/O device for analog and mixed-signal applications. The present invention addresses and solves these particular problems in the art.